Hardware modules of the type mentioned above may be programmed using popular data flow languages. This can create two basic problems:
1. A programmer must become accustomed to programming in data flow languages; multilevel sequential tasks can generally be described only in a complex manner;
2. Large applications and sequential descriptions can be mapped to the desired target technology (synthesized) with the existing translation programs (synthesis tools) only to a certain extent.
In general, applications are partitioned into multiple subapplications, which are then synthesized to the target technology individually (FIG. 1). Each of the individual binary codes is then loaded onto one hardware module. A method described in German Patent 44 16 881, filed on Feb. 8, 1997, makes it possible to use a plurality of partitioned subapplications within a single hardware module by analyzing the time dependence, sequentially requesting the required subapplications from a higher-level load unit via control signals, whereupon the load unit loads the subapplications onto the hardware module.
Existing synthesis tools are capable of mapping program loops onto hardware modules only to a certain extent (FIG. 2 (0201)). FOR loops (0202) are often supported only as primitive loops by fully rolling out the loop onto the resources of the target module, in FIG. 2.
Contrary to FOR loops, WHILE loops (0203) have no constant abort value. Instead, a WHILE loop is evaluated using a condition, whenever interrupt takes place. Therefore, normally (when the condition is not constant), at the time of the synthesis, it is not known when the loop is aborted. Due to their dynamic behavior, these synthesis tools cannot map these loops onto the hardware, e.g., transfer them to a target module, in a fixed manner.
Using conventional synthesis tools, recursions basically cannot be mapped onto hardware if the recursion depth is not known at the time of the synthesis. Mapping may be possible if the recursion depth is known, e.g., constant. When recursion is used, new resources are allocated with each new recursion level. This would mean that new hardware has to be made available with each recursion level, which, however, is dynamically impossible.
Even simple basic structures can be mapped only by synthesis tools when the target module is sufficiently large to offer sufficient resources.
Simple time dependencies (0301) are not partitioned into multiple subapplications by conventional synthesis tools and can therefore be transferred onto a target module as a whole.
Conditional executions (0302) and loops over conditions (0303) can also only be mapped if sufficient resources exist on the target module.